Silicon-based GaAs and optoelectronic devices

Group Leader:JianJun Zhang

Position

Team leader of silicon-based GaAs and optoelectronic devices

Research Direction

the growth of high-quality III-V group materials on silicon substrate compatible with CMOS and solves the problem of the lack of silicon-based laser light sources in silicon-based optoelectronic tech

Team members

The team needs 20 people, including 9 people for epitaxial process development, 2 people for material characterization, 3 people for process management and R&D, 4 people for chip design and testing, and 2 people for customer service. Currently, one postdoctoral researcher and two engineers have been recruited. The team consistently seeks top talents in the fields above, including principal and associate researchers, postdoctoral researchers, and engineers. Contact Information: jjzhang@sslab.org.cn

Potential Market

According to the data from Ovum, the global optical communication device market is experiencing an overall growth trend, with an estimated revenue of $16.6 billion by 2020. In terms of product technology, major optical component manufacturers globally are actively developing active optical chips, devices, and optical module products, achieving speeds of 100Gb/s and above. Domestic enterprises have a high market share in the low-end segment of passive devices and low-speed optical transceiver modules, but there is still much room for improvement in high-end active devices and optical modules. From the perspective of market share, Chinese enterprises are relatively weak. Only one Chinese enterprise ranks among the top ten in the global optical communication device market.

The core of optical communication devices is chips, but chips have always been a shortcoming of the entire Chinese manufacturing industry. At present, the market share of domestic high-end chip products with 25Gb/s and above is less than 5%. Optical communication is an industry with extremely fierce global competition. The two fields of optical fiber and system equipment have entered the oligopoly competition stage, while the field of optical communication devices is still in the era of complete competition with market shares scattered.

The huge cost pressure and challenging market environment have accelerated the restructuring and integration of manufacturers in the optical communication device industry. Foreign manufacturers have continuously expanded their industry chain through acquisitions and mergers, completing technological and business transformation, enabling their products to cover almost all aspects of the optical device and optical module fields. Therefore, the need to develop high-speed silicon-based optical transceiver chips with China's intellectual property rights is very imminent. The smooth implementation and completion of the project will effectively solve this bottleneck problem and help domestic optical communication companies get rid of foreign technology constraints.

Research direction

The main research direction of this project is to achieve the growth of high-quality III-V group materials on silicon substrates compatible with CMOS using epitaxial growth, and ultimately solve the bottleneck problem of the lack of silicon-based laser light sources in silicon-based optoelectronic technology. The team uses the IV/III-V dual-cavity hybrid molecular beam epitaxy system to grow high-quality, commercially-required silicon-based gallium arsenide heteroepitaxial wafers on silicon patterned substrates, and to prepare high-performance silicon-based III-V communication band FP and DFB series quantum dot lasers and optical amplifiers, with the ultimate goal of achieving monolithic integrated high-speed silicon optical transceiver chips. The specific research is as follows:

 

Figure 1 (a) SEM image of the cross-section of a "U" shaped patterned Si substrate. (b) Cross-sectional SEM image of a substrate with a "V" shaped sawtooth structure, constructed after a homogeneous epitaxial silicon buffer layer. (c) SEM image of the sample cross-section after the III-V buffer layer. (d) Physical image of an 8-inch Si(001) patterned substrate.

 

Figure 2 (a) Cross-sectional TEM image of Ge film grown on Si (001). (b) HR-TEM image of the top Ge film grown on Si (001). (c) Cross-sectional TEM image of Si0.2Ge0.8 film grown on Si (001). (d) HR-TEM image of the top Si0.2Ge0.8 film grown on Si (001).
  1. Prepare the pattern on the 8-inch silicon and SOI substrates using the deep ultraviolet stepper lithography on the CMOS process as shown in Figure 1(d). The dry-wet etching process is used to construct a periodic U-shaped grating structure on the substrate as shown in Figure 1(a). On this structure, a uniform V-shaped hole structure with (111) crystal plane is constructed through homoepitaxy of the silicon buffer layer as shown in Figure 1(b), which is used to suppress the extension of anti-phase domains and misfit dislocations during III-V heteroepitaxy. On V-shaped sawtooth structure which can effectively release thermal mismatch in heteroepitaxy, a high-quality GaAs buffer layer can be epitaxially grown as shown in Figure 1(c), thereby obtaining a high-quality silicon-based gallium arsenide heteroepitaxial wafer.
  2. Design and grow silicon-based and SOI-based 1.3 μm InAs/GaAs quantum dot laser structures. Use microfabrication to complete the device preparation. Testing, and performance optimization (power, lifetime, threshold current density, etc.) of silicon-based and SOI-based InAs/GaAs quantum dot series lasers. Ultimately achieving an integrated silicon-based laser that meets commercial requirements.
  3. Design and grow SOI-based embedded communication band III-V quantum dot laser structures. Complete the preparation of laser devices and the coupling of lasers with SOI-based silicon waveguides, ultimately achieving the monolithic integration of high-speed silicon optical transceiver chips.
  4. Customization of 4,6,8 inch Si0.7Ge0.3、 Si0.2Ge0.8 and Ge heteroepitaxial wafers on silicon substrates.